1. Field
Embodiments of the inventive concept relate to a lock detector, a phase locked loop (PLL) circuit including such a lock detector, a method of detecting a lock, and a system including such a lock detector and/or PLL circuit. More particularly, embodiments relate to a lock detector configured to be capable of stably determining a lock state and an unlock state of a PLL circuit, a method of detecting a lock, and a system including such a lock detector and/or PLL circuit.
2. Description of the Related Art
In general, a phase locked loop (PLL) circuit may be a basic circuit included in an electronic system, which may generate an output clock signal having a desired frequency and transmit the output clock signal to internal circuits. The PLL circuit may be applied to many circuits configured to operate in synchronization with a clock signal. Meanwhile, the PLL circuit may continuously compare the phase of a reference clock signal with that of the output clock signal and allow the output clock signal to maintain a predetermined frequency using a frequency correction method.
Typically, circuits configured to receive the output clock signal from the PLL circuit may use the output clock signal only when the PLL circuit is in a lock state. Here, the lock state refers to a state where the phase of the output clock signal is equal to that of the reference clock signal. Since it is difficult to equalize the phase of the output clock signal to that of the reference clock signal, it is determined that the PLL circuit is in the lock state when a phase difference between the output clock signal and the reference clock signal is within a predetermined range. The PLL circuit may include a lock detection circuit configured to determine the lock state or an unlock state.
The lock detection circuit may compare the phase difference between the reference clock signal and the output clock signal with a reference value and determine that the PLL circuit is in the lock state when the phase difference between the reference clock signal and the output clock signal is less than the reference value. When the PLL circuit is in the lock state, internal circuits may receive the output clock signal and use the output clock signal as an internal clock signal.
However, variations in external factors, such as process, voltage, and temperature (PVT) factors may lead to a change in the reference value. For example, the reference value may become less than a value of jitter, which is an output noise typically caused by internal characteristics of the PLL circuit. In this case, when the jitter occurs, the lock detection circuit may mistake the lock state for the unlock state and output a wrong output signal. Conversely, when the reference value is increased due to external factors, the lock detection circuit may mistake the unlock state for the lock state and output a wrong output signal. As described above, when the reference value per se is changed due to the external factors, a malfunction may become highly likely to occur in the PLL circuit, and a system may be unstable.